1. Field of the Invention
The present invention relates to a digital computer system, more particularly to a tag control circuit in a memory access control apparatus provided between a main storage and one or more central processors having a buffer storage therein, the memory apparatus controlling memory access requests to the main storage and operating on tag information for the buffer storage.
2. Description of the Related Art
In a digital computer system including central processor(s), a main storage, and a memory access control apparatus provided between the central processor(s) and the main storage, each central processor is commonly provided with a buffer storage having a considerably faster access time than the main storage, but having a considerably smaller memory capacity.
The central processor can directly access data stored in its buffer storage, which may be identical to that in the main storage, without an access request to the main storage through the memory access control apparatus. This improves the data access time in the central processor.
The data in the buffer storage, which may be frequently used in the central processor, is previously transferred from a certain area in the main storage to an area in the buffer storage in response to an access request from the central processor. The data in the buffer storage may be updated and may also be returned to the main storage upon transfer of new data to the same area of the buffer storage.
In order to manage use of the buffer storage, first and second tag control circuits are provided. The first tag control circuit is provided in the central processor and is called "TAG1". The second tag control circuit is provided in the memory access control apparatus and is called "TAG2". The present invention essentially relates to the second tag control circuit TAG2.
The prior art, which will be explained later in detail with reference to the drawings, suffers from unnecessary communication between the central processor and the memory access control apparatus for managing the buffer memory storage, with a resultant reduction of the performance of the central processor.
The prior art also suffers from poor reliability of judgement of invalidation in the second tag control circuit TAG2 for a faulty data block of the buffer storage, which will be explained in more detail with reference to a specific example.